Simulate to prove your concept

Telelogic® SDL Suite™ offers a rich set of tools for simulation, both for verification and for validation. Verification is performed not only through static analysis, as described above, but also through an automatic exhaustive exploration of the SDL specification, and all included C code. This is done by testing all possible execution paths of the SDL system, during which a number of rules are checked and violations reported (e.g. deadlocks, loops, and exceeded queue length). The result of the verification is presented as an easy-to-follow tree view.

In the validation phase, you confirm that the system does exactly what it is supposed to and nothing else. You can simulate in batch or in interactive mode through a graphical user interface. It is also possible to connect it to another SDL system, or to a TTCN test suite. You can monitor the progress of the simulation graphically and set breakpoints at your convenience. Another of the major application areas of the validation tool is to verify that an SDL system is consistent with an MSC use case by checking whether there is a possible execution path that satisfies the MSC. This provides a powerful way to match your system behavior against e.g. a requirements specification.